阅读下面一段Verilog HDL程序。哪一种说法是不正确的?module basegate (a, b, noto, ando, oro); //模块名,端口列表input a; //输入端口声明input b;output ando; //输出端口声明output noto;output oro;//采用assign语句数据流描述方式assign ando =a & b; //连续赋值语句assign noto = ~a;assign oro =a | b;endmodule //模块结束语句