关于以下程序，下列说法中正确的是module Learn10_2(clk,rst_n,din,pos_clk,neg_clk)input clk,rst_n,din;output pos_clk,neg_clk;reg ctrl_this,ctrl_last;always@(posedge clk or negedge rst_n)beginif(!rst_n)beginctrl_this <= 0;ctrl_last <= 0;endelse beginctrl_this <= din;ctrl_last <=ctrl_thisendendassign pos_clk = ctrl_this&(!ctrl_last)endmodule