请按顺序在下面横线上填上合适的表达式或语句,完成JK触发器的设计,其真值表如下: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY ffJK IS PORT( Cp,J,K: IN STD_LOGIC; q: OUT STD_LOGIC); END ffJK; ARCHITECTURE a OF ffJK IS signal qn : std_logic; Signal tt : std_logic_vector(2 downto 1); Begin Process(____ ) --空(1) begin tt<=______ ;--空(2) if Cp’event and Cp=’0’ then case tt is when “10”=> qn<=‘1’ ; when “01”=> qn<=‘0’ ; when “11”=>__________________________;--空(3) when ______________________________;--空(4) End case; End if; End Process; ________________; --空(5) End a;