在下面横线上填上合适的语句,完成 10 位二进制加法器电路的设计。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ ( ) .ALL; ENTITY ADDER1 IS PORT(A,B:IN STD_LOGIC_VECTOR(9 DOWNTO 0); COUT:OUT STD_LOGIC; SUM:OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); END; ARCHITECTURE JG OF ADDER1 IS SIGNAL ATEMP: STD_LOGIC_VECTOR(10 DOWNTO 0); SIGNAL BTEMP: STD_LOGIC_VECTOR(10 DOWNTO 0); SIGNAL SUMTEMP: STD_LOGIC_VECTOR(10 DOWNTO 0); BEGIN ATEMP<=’0’& A; BTEMP<=’0’& B; SUMTEMP<= ( ) ; SUM<=SUMTEMP ( ) ; COUT<= ( ) ; END;