请将以下三人表决电路的VHDL描述,在QuartusII下,进行编译,并进行仿真,将其仿真波形图与三人表决电路的真值表进行比较说明?(只需上传仿真波形图和真值表) ENTITY vote IS --实体部分 PORT(a,b,c: IN BIT; f: OUT BIT); END ENTITY vote; ARCHITECTURE one OF vote IS --结构体部分 BEGIN f<=(a AND b) OR (a AND c) OR (b AND c); END ARCHITECTURE one;