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【单选题】
已知时钟信号clk的频率为50MHz，下列程序的逻辑功能为（ ）。always@(posedge clk or negedge nreset)begin if(!nreset) begin per_count = 0; clk0 = 0; end else begin if(per_count<6250000) per_count=per_count+1; else begin per_count = 0; clk0=!clk0; end endendA.
8Hz 分频器
B.
4Hz 分频器
C.
移位寄存器型计数器
D.
循环译码器
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