下面程序是一个 10 线- 4 线优先编码器的 VHDL 描述,试补充完整。 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL; ENTITY coder IS PORT ( din : IN STD_LOGIC_VECTOR(________); output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END coder; ARCHITECTURE behav OF ________IS SIGNAL SIN :STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS (_____ ) BEGIN IF (din(9)='0')THEN SIN <= "1001" ; _____________THEN SIN <= "1000" ; ELSIF(din(7)='0') THEN SIN <= "0111"; ELSIF(din(6)='0') THEN SIN <= "0110"; ELSIF(din(5)='0') THEN SIN <= "0101"; ELSIF(din(4)='0') THEN SIN <= "0100"; ELSIF(din(3)='0') THEN SIN <= "0011"; ELSIF(din(2)='0') THEN SIN <= "0010"; ELSIF(din(1)='0') THEN SIN <= "0001"; ELSE ____________; END IF ; END PROCESS ; Output <= sin ; END behav;