在下面横线上或括号中填上合适的语句,完成一个具有三态输出的双 4 选 1 数据选择器的设计。 说明:双 4 选 1 数据选择器,其地址信号共用,且各有一个低电平的使能端。 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY shuangmux41 IS PORT(a: IN std_logic_vector(3 DOWNTO 0); b: IN std_logic_vector(3 DOWNTO 0); sel : IN std_logic_vector(1 DOWNTO 0); en1,en2 : IN std_logic; y1: OUT std_logic); END shuangmux41; ARCHITECTURE art OF shuangmux41 IS BEGIN PROCESS(sel,en1,en2) BEGIN IF en1='0'AND en2='1' THEN CASE sel IS WHEN "00"=>y1<=a(0); WHEN "01"=>y1<=a(1); WHEN "10"=>y1<=a(2); WHEN "11"=>y1<=a(3); WHEN OTHERS=>NULL; END CASE; ( ) en1='1' AND en2='0' THEN CASE ( ) IS WHEN "00"=>y1<=b(0); WHEN "01"=>y1<=b(1); WHEN "10"=>y1<=b(2); WHEN "11"=>y1<=b(3); WHEN OTHERS=>NULL; END CASE; ELSE y1<= ( ) ; END IF; END PROCESS; END;