设计时,采用例化语句完成,已有半加器元件hadd,请补充以下的程序完成设计。 ENTITY ________________ IS PORT (ain ,bin,: IN STD_LOGIC; c ,s : OUT STD_LOGIC ); END; ARCHITECTURE fd1 OF fulladd IS ___________________ hadd PORT ( a ,b : IN STD_LOGIC; c ,s : OUT STD_LOGIC); END ; ... U1: ___________PORT __________(a=>ain ,b=>bin); ...